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工控人家園 綜合討論 RS422 FX1S 串口讀寫一次C235耗時30ms！！！

moecmks

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樓主發(fā)表于: 2017-04-24 19:39

只看樓主 | 小中大

先發(fā) FX1S數據讀報文，PLC接受到信號準備數據放到緩沖區(qū)。然后在用ReadFile從緩沖區(qū)接受一次報文。。。 30 MS左右
這時間正常嗎？還是說我設置有問題？總感覺這樣時間有點長啊。【工控菜鳥一個，放下代碼求老鳥指點一二，有無能提升效率的地方。 ^_^】

復制代碼

#include <Windows.h>
#include "codecb.h"
#include "invariant.h"
#include <assert.h>
#include <tchar.h>
#include "timing.h"
extern HANDLE commport;
_CRT_ALIGN (32)
char ASCII_tonums_RVlut[0xFFFF+1];
void build_ASC_RVlut (void)
{
uint32_t ii;
static BOOL __init = FALSE;
if ( __init == TRUE) return;
__init = TRUE;
ZeroMemory (ASCII_tonums_RVlut, sizeof (ASCII_tonums_RVlut));
for (ii = 0; ii != 0x10000; ii++) {
uint16_t lo = ii & 0x00FF;
uint16_t hi = ii >> 8;
if ( (( lo >= '0' && lo <= '9') || ( lo >= 'A' && lo <= 'F'))
&& (( hi >= '0' && hi <= '9') || ( hi >= 'A' && hi <= 'F')))
{
if ( ( hi >= '0' && hi <= '9'))
ASCII_tonums_RVlut[ii] = hi - '0';
else if ( ( hi >= 'A' && hi <= 'F'))
ASCII_tonums_RVlut[ii] = hi - 'A' + 10;
if ( ( lo >= '0' && lo <= '9'))
ASCII_tonums_RVlut[ii] |= ( ( (unsigned) (lo - '0')) << 4);
else if ( ( lo >= 'A' && lo <= 'F'))
ASCII_tonums_RVlut[ii] |= ( ( (unsigned) (lo - 'A' + 10)) << 4);
}
}
}
BOOL comm_init (int comm_index)
{
DCB dcbs;
COMMTIMEOUTS ct;
BOOL success_io_;
TCHAR comm_buf0[256];
_stprintf (& comm_buf0[0], _T ("//./COM%i"), comm_index);
comm_close ();
commport = CreateFile ( & comm_buf0[0], GENERIC_READ | GENERIC_WRITE, 0,
NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
success_io_ = GetCommState (commport, & dcbs);
assert (success_io_ != FALSE);
dcbs.BaudRate = CBR_9600;
dcbs.fParity = TRUE;
dcbs.Parity = EVENPARITY;
dcbs.StopBits = ONESTOPBIT;
dcbs.ByteSize = 7;
dcbs.fDtrControl = DTR_CONTROL_DISABLE;
dcbs.fRtsControl = RTS_CONTROL_DISABLE;
success_io_ = SetupComm (commport, 2048, 2048);
assert (success_io_ != FALSE);
success_io_ = SetCommState (commport, & dcbs);
assert (success_io_ != FALSE);
// SetTimeOut.
ct.ReadIntervalTimeout = 0x0000FFFF;
ct.ReadTotalTimeoutMultiplier = 0x0000FFFF;
ct.ReadTotalTimeoutConstant = 0xFFFFFFFE;
ct.WriteTotalTimeoutMultiplier = 0x0000FFFF;
ct.WriteTotalTimeoutConstant = 0xFFFFFFFE;
success_io_ = SetCommTimeouts (commport, &ct);
assert (success_io_ != FALSE);
success_io_ = SetupComm (commport, 2400, 2400);
assert (success_io_ != FALSE);
success_io_ = PurgeComm (commport, PURGE_RXABORT | PURGE_TXCLEAR | PURGE_RXCLEAR | PURGE_TXABORT);
assert (success_io_ != FALSE);
build_ASC_RVlut ();
timing_init48 ();
INIT_WSCCRSEC__;
}
void comm_close (void)
{
if (commport != INVALID_HANDLE_VALUE)
{
PurgeComm (commport, PURGE_RXABORT | PURGE_TXCLEAR | PURGE_RXCLEAR | PURGE_TXABORT);
CloseHandle (commport);
}
commport = INVALID_HANDLE_VALUE;
}
int8_t readOYB (int16_t e_addr) {
struct read_section2 rdsec;
char varsbuf[128];
int isr = 0;
int tm_numbs = 0;
uint16_t rv_numbs = 0;
BOOL io_success_;
DWORD rv_numbs2 = 0;
/* prepare Output-register read_section. */
isr = fx1s_makersecb ( & rdsec, FX1S_REGISTER_FIELD_Y_OUT,
& rv_numbs, FX1S_VERSION_30MR, e_addr);
assert (isr == FX1S_OK);
/* write Output-register read-code. */
io_success_ = WriteFile (commport, & rdsec,
sizeof(struct read_section), & tm_numbs, NULL);
assert (io_success_ != FALSE);
assert (tm_numbs == sizeof(struct read_section));
io_success_ = ReadFile (commport, & varsbuf[0], rv_numbs, & rv_numbs2, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs2 == rv_numbs);
assert (varsbuf[0] == SECTION_LINK_STX);
return ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[1]];
}
void setOYB (int16_t e_addr, int8_t val) {
char varsbuf[128];
int isr = 0;
int tm_numbs = 0;
uint16_t rv_numbs = 0;
BOOL io_success_;
DWORD rv_numbs2 = 0;
/* prepare Output-register write_section. */
isr = fx1s_makewsecb (& varsbuf[0], & val, FX1S_REGISTER_FIELD_Y_OUT,
& rv_numbs, FX1S_VERSION_30MR, e_addr);
assert (isr == FX1S_OK);
/* write Output-register write-code. */
io_success_ = WriteFile (commport, & varsbuf[0],
rv_numbs, & tm_numbs, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs == tm_numbs);
io_success_ = ReadFile (commport, & varsbuf[0], 1, & rv_numbs2, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs2 == 1);
assert (varsbuf[0] == SECTION_LINK_ACK);
}
static __forceinline
int8_t readRELAY_M (int16_t addr) {
struct read_section2 rdsec;
char varsbuf[128];
int isr = 0;
int tm_numbs = 0;
uint16_t rv_numbs = 0;
BOOL io_success_;
DWORD rv_numbs2;
isr = fx1s_makersecb ( & rdsec, FX1S_REGISTER_FIELD_M,
& rv_numbs, FX1S_VERSION_14MR, addr);
assert (isr == FX1S_OK);
io_success_ = WriteFile (commport, & rdsec,
sizeof(struct read_section), & tm_numbs, NULL);
assert (io_success_ != FALSE);
assert (tm_numbs == sizeof(struct read_section));
io_success_ = ReadFile (commport, & varsbuf[0], rv_numbs, & rv_numbs2, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs2 == rv_numbs);
assert (varsbuf[0] == SECTION_LINK_STX);
return ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[1]];
}
static __forceinline
void writeRELAY_M (uint16_t addr, int8_t val) {
char varsbuf[128];
int isr = 0;
int tm_numbs = 0;
uint16_t rv_numbs = 0;
BOOL io_success_;
DWORD rv_numbs2;
/* prepare Output-register write_section. */
isr = fx1s_makewsecb (& varsbuf[0], & val, FX1S_REGISTER_FIELD_M,
& rv_numbs, FX1S_VERSION_14MR, addr);
assert (isr == FX1S_OK);
/* write Output-register write-code. */
io_success_ = WriteFile (commport, & varsbuf[0],
rv_numbs, & tm_numbs, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs == tm_numbs);
io_success_ = ReadFile (commport, & varsbuf[0], 1, & rv_numbs2, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs2 == 1);
assert (varsbuf[0] == SECTION_LINK_ACK);
}
void plc_force_close_ (void) {
BYTE obt;
/* force close PLC [by M8037] **/
obt = readRELAY_M (8037);
writeRELAY_M (8037, obt | 0x20);
}
void plc_force_open_ (void) {
BYTE obt;
/* force open PLC [by M8035/M8036/M8037] **/
obt = readRELAY_M (8037);
obt &= ~(1 << (8037 & 7));
writeRELAY_M (8037, obt);
obt = readRELAY_M (8035);
obt |= (11 << (8035 & 7));
writeRELAY_M (8035, obt);
}
void plc_set_pulse235_ (uint32_t val) {
int isr = 0;
char varsbuf[128];
uint16_t rv_numbs = 0;
DWORD rv_numbs2 = 0;
DWORD rv_numbs3 = 0;
BOOL io_success_;
isr = fx1s_makewsecb (& varsbuf[0], & val, FX1S_REGISTER_FIELD_C32,
& rv_numbs, FX1S_VERSION_14MR, PULSE_ENCODER_ADDR);
assert (isr == FX1S_OK);
rv_numbs2 = rv_numbs;
io_success_ = WriteFile (commport, & varsbuf[0], rv_numbs, & rv_numbs3, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs2 == rv_numbs3);
io_success_ = ReadFile (commport, & varsbuf[0], 1, & rv_numbs2, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs2 == 1);
assert (varsbuf[0] == SECTION_LINK_ACK);
}
uint32_t plc_get_pulse235_ (void) {
union {
char bgroup[4];
int32_t inter;
} cc_timing;
BOOL io_success_;
DWORD rv_numbs = 0;
BYTE varsbuf[128];
io_success_ = WriteFile (commport, & g_crs2_pulse235.rsc, sizeof (struct read_section), & rv_numbs, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs == sizeof (struct read_section));
io_success_ = ReadFile (commport, & varsbuf [0], g_crs2_pulse235.rsc_cnt, & rv_numbs, NULL);
assert (io_success_ != FALSE);
assert (rv_numbs == g_crs2_pulse235.rsc_cnt);
assert (varsbuf[0] == SECTION_LINK_STX);
assert (varsbuf[9] == SECTION_LINK_ETX);
cc_timing.bgroup[0] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[1]];
cc_timing.bgroup[1] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[3]];
cc_timing.bgroup[2] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[5]];
cc_timing.bgroup[3] = ASCII_tonums_RVlut[ *(uint16_t *)& varsbuf[7]];
return cc_timing.inter;
}

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1樓發(fā)表于: 2017-04-24 19:48

只看該作者 | 小中大

FX1S 報文編解碼

復制代碼

/*-
* Copyright (c) 2017 moecmks
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRCMD, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#if !defined (codec_included_MOECMKS)
#define codec_included_MOECMKS
/*
* fx1s read/write codec.
* simple, each read a current register size unit memory
* more information, please refer to the PLC manual and Internet resources.
*/
#if defined (__cplusplus) /** __cplusplus */
extern "C" {
#endif /** __cplusplus */
/* Portable fixed length ***/
#include "stdint.h"
/*
* errror code
*/
#define FX1S_RANGE 1
#define FX1S_FAIL 2
#define FX1S_KFAIL 3
#define FX1S_UNKN 4
#define FX1S_LIMIT 5
#define FX1S_NAK 6
#define FX1S_ACK 7
#define FX1S_PARA 8
#define FX1S_INCOP 9
#define FX1S_OK 0
/*
* version control
*/
enum FX1S_VERSION {
FX1S_VERSION_10MR = 0,
FX1S_VERSION_14MR,
FX1S_VERSION_20MR,
FX1S_VERSION_30MR,
FX1S_VERSION_OVERFLAGS
};
/*
* register field.
* Ignore T bit register and set register.
* Ignore C bit register
*/
enum FX1S_REGISTER_FIELD {
FX1S_REGISTER_FIELD_S = 0,
FX1S_REGISTER_FIELD_X,
FX1S_REGISTER_FIELD_Y_OUT,
FX1S_REGISTER_FIELD_Y_PLS,
FX1S_REGISTER_FIELD_D,
FX1S_REGISTER_FIELD_T,
FX1S_REGISTER_FIELD_M,
FX1S_REGISTER_FIELD_C16,
FX1S_REGISTER_FIELD_C32,
FX1S_REGISTER_FIELD_CRESET
};
/*
* section .link code
*/
#define SECTION_LINK_STX 0x02 /* PLC info-section begin flags. */
#define SECTION_LINK_ETX 0x03 /* PLC info-section end flags .***/
#define SECTION_LINK_EOT 0x03 /* .***/
#define SECTION_LINK_ENQ 0x05 /* PLC only test enable */
#define SECTION_LINK_ACK 0x06 /* PLC reply "can do" */
#define SECTION_LINK_LF 0x0A /* .***/
#define SECTION_LINK_CL 0x0C /* .***/
#define SECTION_LINK_CR 0x0D /* .***/
#define SECTION_LINK_NAK 0x15 /* PLC reply "bad things" */
/*
* section cmdion.
*/
#define SECTION_CMD_READ '0' /* .***/
#define SECTION_CMD_WRITE '1' /* .***/
#define SECTION_CMD_FORCE_ON '7' /* .***/
#define SECTION_CMD_FORCE_OFF '8' /* .***/
/*
* read section
*/
struct read_section {
uint8_t stx; /* read_section's stdhead. always SECTIOM_LINK_STX */
uint8_t cmd; /* read_section's cmd always SECTIOM_CMD_READ */
uint8_t unit_address[4]; /* read_section's address*/
uint8_t numb[2]; /* read's byte count. simple always one */
uint8_t etx; /* read_section's stdend. always SECTION_LINK_ETX */
uint8_t crc[2]; /* correcting code*/
};
/*
* read section2
*/
struct read_section2 {
uint8_t stx; /* read_section's stdhead. always SECTIOM_LINK_STX */
uint8_t cmd; /* read_section's cmd always SECTIOM_CMD_READ */
uint8_t unit_address[4]; /* read_section's address*/
uint8_t numb[2]; /* read's byte count. simple always one */
uint8_t etx; /* read_section's stdend. always SECTION_LINK_ETX */
uint8_t crc[2]; /* correcting code*/
uint8_t crce; /* easy to read..**/
uint16_t opbsize; /******/
uint8_t opboff; /* for bit register(X, Y, M.) **/
uint16_t opbaddr; /* easy to read. **/
};
/*
* write section
*/
struct write_section {
uint8_t stx; /* write_section's stdhead. always SECTIOM_LINK_STX */
uint8_t cmd; /* write_section's cmd always SECTIOM_CMD_WRITE */
uint8_t unit_address[4]; /* write_section's address*/
uint8_t numb[2]; /* write's byte count.. must <= 64 */
uint8_t etx; /* write_section's stdend. */
uint8_t crc[2]; /* correcting code*/
uint8_t crce; /* easy to read..**/
uint8_t obpoff; /* for bit register(X, Y, M.) **/
uint16_t opbaddr; /* easy to read. **/
};
/*
* force section
*/
struct force_section {
uint8_t stx; /* force_section's stdhead. always SECTIOM_LINK_STX */
uint8_t cmd; /* force_section's cmd always SECTIOM_CMD_FORCE_OFF or SECTIOM_CMD_FORCE_ON */
uint8_t unit_address[4]; /* force_section's address*/
uint8_t etx; /* force_section's stdend. */
uint8_t crc[2]; /* correcting code*/
};
/*
* Accept the write section is very simple,
* if successful send SECTION_LINK_ACK otherwise SECTION_LINK_NAK
*/
int fx1s_makersecb (struct read_section2 *rsec, /* write to the serial port, use the size of the read_section */
enum FX1S_REGISTER_FIELD rf, uint16_t *rvap_size,
enum FX1S_VERSION ver, uint16_t address);
int fx1s_makewsecb (void *wsec, /* Variable size structure, so use void *, please understand **/
void *spval,
enum FX1S_REGISTER_FIELD rf, uint16_t *wsec_size,
enum FX1S_VERSION ver, uint16_t address);
int fx1s_makefsecb (struct force_section *fsec,
enum FX1S_REGISTER_FIELD rf,
enum FX1S_VERSION ver, uint16_t address);
#if defined (__cplusplus) /** __cplusplus */
}
#endif /** __cplusplus */
#endif /* codec_included_MOECMKS */

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2樓發(fā)表于: 2017-04-24 19:52

只看該作者 | 小中大

復制代碼

/*-
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <assert.h>
#include <string.h>
#include "codecb.h"
/* Convert characters to specific number - noexport */
static
char ascii_to_num (char ch) {
/* e.g.
* source '9' -> target 9
* source 'A' -> target 10
* source '1' -> target 1
* source 'a' -> (nondone, Don't use lowercase letters in fx1s-14mr-001).
*/
if (ch >= '0' && ch <= '9')
return (ch - '0');
if (ch >= 'A' && ch <= 'F')
return (ch - ('A' - 10));
else
assert (0);
return ch;
}
/* Convert number to specific characters - noexport */
static
char num_to_ascii (char ch) {
/* e.g.
* source 9 -> target '9'
* source A -> target '0'
* source 1 -> target '1'
* source a -> (nondone, Don't use lowercase letters in fx1s-14mr-001).
*/
if (ch >= 0x00 && ch <= 0x09)
return (ch + '0');
if (ch >= 0x0A && ch <= 0x0F)
return (ch + ('A' - 10));
else
assert (0);
return ch;
}
/* XXX:L-endian.
*/
static
uint16_t vailed8 (uint16_t nums) {
/* e.g.
* 1234 vailed.
* 9000 invailed.
* 1007 vailed.
* 1811 invailed.
* 0 ~ 65535
*/
uint16_t d0 = nums % 10 >> 0;
uint16_t d1 = nums % 100 / 10;
uint16_t d2 = nums % 1000 / 100;
uint16_t d3 = nums % 10000 / 1000;
if ( d0 > 7 || d1 > 7)
return -1;
if ( d2 > 7)
return -1;
return d0 + d1 * 8 + d2 * 8 * 8 + d3 * 8 * 8 * 8;
}
static
uint8_t fxcrc_adjust (unsigned char *crcbuf, uint32_t num) {
uint32_t s= 0;
uint32_t st = 0;
for (; s != num; s++)
st += crcbuf[s];
/* we only save lowest bit's byte **/
return st & 0xFF;
}
static /* we not check numb cross register **.**/
uint32_t fxcalc_addru (enum FXREGS_FIELD reg, uint16_t addr,
enum FX1S_VERSION ver,
uint16_t *opbsize,
uint16_t *raddr, unsigned char *dboff) {
static const /* XXX:enum constant dependence **/
uint16_t xmax_tab[4] = { 6, 8, 12, 16 };
static const /* XXX:enum constant dependence **/
uint16_t ymax_tab[4] = { 4, 6, 8, 14 };
uint16_t addr0 = 0x00A0;
uint16_t eig = vailed8 (addr);
uint8_t off = -1;
uint32_t opbsize0 = 2;
switch (reg) {
case FX1S_REGISTER_FIELD_D:
if (addr <= 127 && addr == addr) /* numbers: 128, normal use */
addr0 = 0x1000 + addr * 2;
else if (addr <= 255) /* numbers: 128, save use */
addr0 = 0x1000 + addr * 2;
else if (addr >= 1000 && addr <= 2499) /* numbers: 1500, file register */
addr0 = 0x1000 + addr * 2;
else if (addr >= 8000 && addr <= 8255) /* numbers: 256, special IO port */
addr0 = 0x0E00 + (addr - 8000) * 2;
else /* Illegal access */
return FX1S_RANGE;
break;
case FX1S_REGISTER_FIELD_X:
/*
* Check the number of available X-coils according to the PLC version
*/
if ((eig = vailed8 (addr)) == -1
|| (eig >= xmax_tab[ver]) )
return FX1S_PARA;
addr0 = 0x0080 + eig / 8;
off = eig & 7;
opbsize0 = 1;
break;
case FX1S_REGISTER_FIELD_Y_PLS:
addr0 += 0x0200;
case FX1S_REGISTER_FIELD_Y_OUT:
/*
* Check the number of available Y-coils according to the PLC version
*/
if ((eig = vailed8 (addr)) == -1)
return FX1S_PARA;
addr0 += eig / 8;
off = eig & 7;
opbsize0 = 1;
break;
case FX1S_REGISTER_FIELD_S:
if ((addr >= 128)) /* numbers:128, status register **/
return FX1S_RANGE;
addr0 = addr / 8;
off = addr & 7;
opbsize0 = 1;
break;
case FX1S_REGISTER_FIELD_T:
if ( (addr <= 63)) /* numbers:64, 100ms or 10ms M8028/D8030/D8031 **/
addr0 = 0x0800 + addr * 2;
else
return FX1S_RANGE;
break;
case FX1S_REGISTER_FIELD_M:
if (addr < 384) /* numbers: 384, normal use */
addr0 = 0x0100 + addr / 8;
else if (addr < 512) /* numbers: 512, save use */
addr0 = 0x0100 + addr / 8;
else if (addr >= 8000 && addr < 8256) /* numbers: 256, special IO port */
addr0 = 0x01E0 + (addr - 8000) / 8;
else /* Illegal access */
return FX1S_RANGE;
off = addr & 7;
opbsize0 = 1;
break;
case FX1S_REGISTER_FIELD_C16:
if (addr < 16) /* numbers: 16, normal use */
addr0 = 0x0A00 + addr * 2;
else if (addr < 32) /* numbers: 16, save use */
addr0 = 0x0A00 + addr * 2;
else /* Illegal access */
return FX1S_RANGE;
break;
case FX1S_REGISTER_FIELD_C32:
/* for C32 high speed registers,
* we only perform some basic checks, please note
**/
if (addr > 200 && addr <= 255)
addr0 = 0x0C00 + (addr - 200) * 4;
else /* Illegal access */
return FX1S_RANGE;
opbsize0 = 4;
break;
case FX1S_REGISTER_FIELD_CRESET:
if (addr <= 255)
addr0 = 0x03C0 + addr / 8;
else /* Illegal access */
return FX1S_RANGE;
opbsize0 = 1;
break;
default:
return FX1S_PARA;
}
*raddr = addr0;
*dboff = off;
*opbsize = opbsize0;
return FX1S_OK;
}
int fx1s_makersecb (struct read_section2 *rsec, /* write to the serial port, use the size of the read_section */
enum FX1S_REGISTER_FIELD rf, uint16_t *rvap_size,
enum FX1S_VERSION ver, uint16_t address)
{
struct read_section2 sec;
uint32_t e;
/** phase 1:fill stdhead/stdend flags and cmd, rread count,s */
sec.stx = SECTION_LINK_STX;
sec.etx = SECTION_LINK_ETX;
sec.cmd = SECTION_CMD_READ;
/** phase 2:calc address for register and current PLC version */
e = fxcalc_addru (rf, address, ver, & sec.opbsize, & sec.opbaddr, & sec.opboff);
if (e != FX1S_OK)
return e;
else
*rvap_size = sizeof (sec.stx) +
sizeof (sec.crc)+ sizeof (sec.etx) + sec.opbsize * 2;
/** phase 3:fill numb ascii, * */
sec.numb[0] = num_to_ascii ( (sec.opbsize & 0xF0) >>4);
sec.numb[1] = num_to_ascii ( (sec.opbsize & 0x0F) >>0);
/** phase 4:fill address ascii, * */
sec.unit_address[0] = num_to_ascii ( (sec.opbaddr & 0xF000) >>12);
sec.unit_address[1] = num_to_ascii ( (sec.opbaddr & 0x0F00) >> 8);
sec.unit_address[2] = num_to_ascii ( (sec.opbaddr & 0x00F0) >> 4);
sec.unit_address[3] = num_to_ascii ( (sec.opbaddr & 0x000F) >> 0);
/** phase 5:crc adjust, fill ascii buf * */
sec.crce = fxcrc_adjust (& sec.cmd, sizeof (sec.cmd) + sizeof (sec.unit_address)
+ sizeof (sec.numb)
+ sizeof (sec.etx));
sec.crc[0] = num_to_ascii ( (sec.crce & 0xF0) >> 4);
sec.crc[1] = num_to_ascii ( (sec.crce & 0x0F) >> 0);
memcpy (rsec, & sec, sizeof (sec));
return FX1S_OK;
}
int fx1s_makewsecb (void *wsec, /* Variable size structure, so use void *, please understand **/
void *buf, /* wsec size == sizeof(wc) * 2 **/
enum FX1S_REGISTER_FIELD rf, uint16_t *wsec_size,
enum FX1S_VERSION ver, uint16_t address)
{
uint16_t opbsize, opbaddr;
char obpoff;
char varsbuf[256];
char *as = buf, cs;
uint32_t e;
uint32_t s = 0;
struct write_section *secp = wsec;
struct write_section *secdp = (void *)varsbuf;
/** phase 1:fill stdhead flags and cmd */
secdp->stx = SECTION_LINK_STX;
secdp->cmd = SECTION_CMD_WRITE;
/** phase 2:calc address for register and current PLC version */
e = fxcalc_addru (rf, address, ver, & opbsize, & opbaddr, & obpoff);
if (e != FX1S_OK)
return e;
else
*wsec_size = sizeof (struct write_section) + opbsize * 2;
/** phase 3:fill numb ascii, * */
secdp->numb[0] = num_to_ascii ( (opbsize & 0xF0) >>4);
secdp->numb[1] = num_to_ascii ( (opbsize & 0x0F) >>0);
/** phase 4:fill address ascii, * */
secdp->unit_address[0] = num_to_ascii ( (opbaddr & 0xF000) >>12);
secdp->unit_address[1] = num_to_ascii ( (opbaddr & 0x0F00) >> 8);
secdp->unit_address[2] = num_to_ascii ( (opbaddr & 0x00F0) >> 4);
secdp->unit_address[3] = num_to_ascii ( (opbaddr & 0x000F) >> 0);
/** phase 5:fill variable buffer, * */
for ( ; s != opbsize; s++) {
unsigned char temp = as[s];
char tmphi = num_to_ascii (temp >> 4);
char tmplo = num_to_ascii (temp & 15);
secdp->numb[2+s*2+0] = tmphi;
secdp->numb[2+s*2+1] = tmplo;
}
/** phase 6:crc adjust, fill ascii buf * */
secdp->numb[2+opbsize*2] = SECTION_LINK_ETX;
cs = fxcrc_adjust (& secdp->cmd, opbsize * 2 + sizeof (secp->cmd) + sizeof (secp->unit_address)
+ sizeof (secp->numb)
+ sizeof (secp->etx));
secdp->numb[2+opbsize*2+1] = num_to_ascii ( (cs & 0xF0) >> 4);
secdp->numb[2+opbsize*2+2] = num_to_ascii ( (cs & 0x0F) >> 0);
memcpy (wsec, & varsbuf, *wsec_size);
return FX1S_OK;
}
uint32_t fx1s_cmprvpack (void *raccbuf, /* Variable size structure, so use void *, please understand **/
uint16_t rc, void **ascii_buf, uint16_t *opbsize
, uint16_t *stdpos)
{
char *varsbuf = raccbuf;
uint16_t c = 0;
char stx_find = 0;
uint16_t stdpos0 = -1;
/* we find SECTION_LINK_NAK or SECTION_LINK_STX at first **/
for (; c != rc; c++)
{
if (varsbuf[c] == SECTION_LINK_NAK)
return FX1S_NAK;
if (varsbuf[c] == SECTION_LINK_STX)
{
/* second, we check SECTION_LINK_ETX in buffer **/
stx_find = 1;
stdpos0 = c + 1;
}
if (varsbuf[c] == SECTION_LINK_ETX && stx_find == 1)
{
/* exist CRC byte ??**/
if ((c + 2) >= rc)
return FX1S_INCOP;
/* calculate, compare the CRC code **/
{
# if 0
# else
*ascii_buf = & varsbuf[stdpos0];
*opbsize = c - stdpos0;
*stdpos = stdpos0;
return FX1S_OK;
# endif
}
}
}
return FX1S_INCOP;
}
uint32_t fx1s_decrvsec (void *raccbuf, void *sbuf, uint16_t opbasize) {
char *varsbuf = raccbuf;
char *ssbuf = sbuf;
uint16_t c = 0;
if (opbasize % 2 == 1)
return FX1S_INCOP;
if (opbasize == 0)
return FX1S_PARA;
for ( ; c != opbasize; c += 2)
{
char tmphi = ascii_to_num (varsbuf[c]) << 4;
char tmplo = ascii_to_num (varsbuf[c+1]);
char temp = (tmphi & 0xF0) | (tmplo & 0x0F);
ssbuf[c>>1] = temp;
}
return FX1S_OK;
}

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